D触发器VHDL语言描述 clk'event的意义

clk'event是指信号clk是否发生跳变，若发生了则返回ture，否则为假，
clk=‘1’是跳变后clk为高电平。合起来就是当clk信号的上升沿则....

library ieee;
use ieee.std_logic_1164.all;
entity d_chufaqi is
port ( clk:in std_logic;
   d:in std_logic;
   q:out std_logic);
end d_chufaqi;
 
architecture d_chufaqi_arch of d_chufaqi is
 
begin
 process (clk,d)
 begin
  if(clk='1' and clk'event) then 
   q<=d;
  end if;
 end process ;
end d_chufaqi_arch;